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onebitfulladder
- This a one bit full adder design
Adder4
- 本设计是设计了一个4位全加器的内容,是由4个一位全加器串联而成的-The design is to design a full adder 4 content, is one of four full adder in series from the
16weijiafaqi
- 本程序是在一位全加器的基础上设计一个16位的加法器,用Verilog HDL语言描述.-This procedure is a full-adder based on the design of a 16-bit adder, using Verilog HDL language to describe.
VHDL01
- 全加器仿真程序. 大家可以参考下 ,本人检查无误。无毒。如有问题,请来信咨询。-Full adder simulation program. You can refer to, I check the accuracy. Non-toxic. If you have any questions, please contact us advice.
VHDL03
- 全加器仿真程序代码,本人亲自测试,代码简单,安全无毒。放心下载和使用。-Full adder simulation code, I personally tested the code simple, safe non-toxic. Ease to download and use.
full_add
- 这是一个全加器,有三个输入,有两个输出,输入分别是两个加数,一个进位,输出分别是和,进位-This is a full adder, three input, two output, input is represented by two summand, a binary output, respectively and, binary
Desktop
- VHDL code for 16 byte ROM & n bit comparator & a full adder
tristate
- VHDL code for a full adder and n bit full adder a tri state buffer and a flip flop
testZ
- 八位加法器的原理图实现方法和一位半加器 全加器的原理图实现-Eight adder schematic diagram of the method and a half adder full adder schematic diagram of the realization of
full_adder
- testing for full adder
fulladder4
- VHDL图形文件实现的4位全加器,希望对大家有用!-VHDL graphics files to achieve four full adder, in the hope that useful!
vhdl
- full adder is implemented using VHDL
FullAdderusingHalfAdder
- full adder project conating source code and simulation results.
myadd32
- 32位全程加法器,可以进行移位操作及多位多输入多输出加减法-32-bit full adder, shift operations can be carried out and a number of multiple-input multiple-output addition and subtraction
FA_4
- Full adder 4 vhdl code
FA_8
- Full adder 8 vhdl code
FA_16
- Full adder 16 vhdl code
FA_32
- Full adder 32 vhdl code
half_adder
- 一个半加器,具有进位和位数相加的基本功能,可作为全加器的基本模块-One and a half adder with binary and the sum of the basic functions of the median, full adder can be used as the basic module
f_adder8
- fpga八位全加器(vhdl语言),由画图法制作,将八个一位全加器(由一位半加器组成)组合制成-fpga eight full adder (vhdl language)